The present invention is based on the problem that circuit units, particularly memory chips with circuit units to be tested, must be subjected to extensive tests after production in order to meet the increasingly high quality requirements of the users. In this context, different test stages are distinguished where, beginning at a so-called front end, memory chips or circuits units to be tested are tested at a time when the wafer carrying the circuit units to be tested has not been sawn and the circuit units to be tested have not yet been packaged in a package.
This front-end test method has the advantage that specific positions on the circuit unit to be tested can be electrically contacted with pointed needles (contact needles) and voltages and currents can thus be detected precisely.
Disadvantageously, these contact points, also called test points, are no longer accessible from the outside when the circuit unit to be tested is packaged in a package.
During the further testing, a procedure called burn-in subsequently takes place, where the circuit unit to be tested is exposed, for example, but not exclusively to high temperatures and high voltages which results in artificial aging. It should be pointed out that during the aging of circuit units to be tested, a characteristic curve occurs when an error rate of the memory chips to be tested is plotted against time.
This characteristic curve is also called a bathtub curve, i.e. there is a high error rate at the beginning of the life of a memory chip to be tested whereas subsequently a low constant error rate is maintained over a relatively long time, which, finally, rises again. In order to reach a range of a long-lasting constant low error rate after a production of memory chips, the memory chips must be artificially aged and during this artificial aging, memory chips or circuit units which become faulty must be sorted out before delivery to the user.
In artificial aging or a burn-in process, a high voltage is conventionally achieved by actuation of a special test mode where internal voltage stabilizers are switched off and voltages are thus scaled with high operating voltages applied from the outside. During a burn-in procedure, a number of memory chips are generally contacted simultaneously via a socket connecting unit on a so-called burn-in board.
FIG. 3 shows a conventional memory chip with a circuit unit 100 to be tested which is connected to a test device 105 by means of a connecting unit 104. The circuit unit to be tested simultaneously supplies data on one or more test lines 111a-111n (typically, n=16 or n=32). It should be pointed out that the number n of test lines is not essential for understanding the invention.
If the circuit unit to be tested or the memory chip to be tested is to be tested in a conventional manner, a test line must be run to each connecting pin of the connecting unit 104 and the information provided thereon must then be checked for its correctness. This is done, for example, by means of a so-called comparator unit.
A simplification of conventional methods is obtained by the circuit unit to be tested internally comparing actual data with nominal data and signaling the result of this comparison at a single connecting pin of the connecting unit 104, in each case a number of bits being compared simultaneously and a result of this evaluation being logically combined.
This results in a data compression which advantageously saves a large number of comparator units and test lines. During this process, a number of data outputs, burst bits, addresses etc. can be compressed.
Referring to the so-called front end described above, a result achieved is not output at one but at a number of connecting pins of the connecting unit 104 which results in the advantage that an error in the circuit unit 100 to be tested can be located more accurately if, for example, different areas of the circuit unit to be tested output their test result at different connecting pins.
Such locating of errors is advantageously not required in a burn-in procedure since circuit units tested as faulty are generally sorted out during the artificial aging of the circuit units to be tested.
Disadvantageously, however, no further method of data compression is provided for a burn-in procedure or, respectively, no two different data compression methods are generally implemented, so that (chip) area is not unnecessarily used on the circuit unit to be tested. This has the disadvantageous result that data compression occurs at a number of connecting pins of the connecting unit 104 even in a burn-in procedure.
This results in the further disadvantage that a number of comparator lines must be run to each of the socket units on the burn-in board which either restricts the number of socket units or limits the width of conductor track.